(1) Field of the Invention
The invention relates to a method to form a split gate, flash memory cell, and, more particularly, to a split gate, flash memory cell having an L-shaped word line gate with improved process capability.
(2) Description of the Prior Art
Flash memory is an improved version of electrically erasable, programmable read-only memory (EEPROM) which is capable of block-by-block erasing. Flash memory is used in many applications that require programmability with no loss of memory data during power down.
A flash memory transistor comprises a floating gate and a control, or word line, gate. The state of the flash memory transistor is programmed by charging or discharging the floating gate through a control gate. The charge-state of the floating gate, in turn, controls the threshold voltage of the cell transistor. The word line gate can be used to couple a large voltage onto the floating gate for programming or erasing. During a transistor read, a reading voltage is forced onto the word line gate. The presence or absence of drain current is then used to determine the state of the transistor.
A particular form of a flash transistor that is known in the art as a split gate flash. In a split gate flash, the word line gate is formed to both couple voltage onto the floating gate and to control a channel region of the transistor. To accomplish this, the word line gate is physically formed directly overlying the substrate and overlying, or next to, the floating gate. By comparison, a stacked gate flash comprises a word line gate overlying a floating gate where only the floating gate directly overlies the substrate channel. The split gate flash exhibits an improved performance over the stacked gate flash. Specifically, the split gate flash can be constructed to prevent over erasing that occurs in the stacked gate flash.
Referring now to FIGS. 1 through 4, a split gate, flash cell of the prior art is illustrated. Referring first to FIG. 1, a partially completed flash memory cell is shown. It is typical in the art to form a flash cell comprising a pair of transistors. In this case, the transistors are configured to share a common source region 24. The flash cell, at this point in the fabrication process, comprises a substrate 10. A pair of floating gates is formed overlying the substrate 10. The floating gates each comprise a polysilicon layer 18 overlying a gate oxide layer 14. A source plug 26 is used in this example to contact the source region 24. The source plug 26 comprises a conductive material and is isolated from the floating gate polysilicon 18 by an oxide layer 22. Additional oxide layers 30 and 34 create a composite barrier comprising the floating gate pair 18 and 14 and the source plug 26. A dielectric layer 38 is formed overlying the floating gates 30, 18, and 14, and the source plug 34 and 26. A second polysilicon layer 42 is then deposited overlying the dielectric layer 38.
Referring now to FIG. 2, the second polysilicon layer 42 is then anisotropically etched to form spacers on the vertical surfaces of the dielectric layer 38. This technique forms word line gates 42 and 38 that overlie the substrate 10 to thereby control a channel region of the substrate 10. In addition, the word line gates 42 and 38 are adjacent to the floating gates 18 and 14 so that the word line gates can couple voltage onto the floating gates for programming cell states. This technique is particularly useful for fabricating flash memory cells since it does not require a masking step. Therefore, the flash cell size can be shrunk independently with respect to the word line feature.
Referring now to FIG. 3, in a subsequent processing step, dielectric spacers 46 are formed on the side wall surfaces of the word line gates 42 and 38. These dielectric spacers 46 are used to facilitate a self-aligned silicide (salicide) process. It is desirable to form a metal silicide on the word line gate conductor 42 and on drain side bit lines 50 to reduce parasitic resistance. In a salicide process, a metal film is deposited overlying the wafer surface. A high temperature anneal is then performed. During the anneal process, the metal will react with any silicon or polysilicon that is in contact with the metal to form a metal silicide film. Following the anneal, the unreacted metal film is removed.
Referring now to FIG. 4, the resulting metal silicide film 54 is shown formed on the word line conductor 42 and on the drain bit lines 50. Note that a silicide short 58 is also illustrated. A silicide short 58 occurs when the dielectric spacers 46 that separate polysilicon 42 and silicon areas 10 are too small. In this case, the lower spacers 46 have a height Y.
In the prior art example, there are two significant problems. First, the word line gate conductors 42 are formed as spacers on the vertical side wall of the dielectric layer 38 as described above. However, it is not easy to control the channel length X of the word line transistor 42 and 38 using this method. This is especially true due to variations in the heights of shallow trench isolations (STI) across the integrated circuit wafer. These variations in STI height make it necessary to over etch the second polysilicon during the formation of the word line spacers 42 to insure that there is no residue. However, this over etch directly impacts the width X of the word line channel.
The second problem is the aforementioned silicide shorting, or bridging. If the dielectric spacer 46 has inadequate height Y or width, then bridging 58 will occur. Further, a low profile of the word line spacer 42 increases the problem of forming adequate dielectric spacers 46. It is difficult to resolve this problem to achieve consistent process results.
Several prior art inventions relate to split gate flash devices. U.S. Pat. No. 6,312,989 B1 to Hsieh et al discloses a split gate flash memory cell having a source plug and word lines comprising polysilicon spacers. U.S. Pat. No. 6,271,088 B1 to Liu et al teaches a method to form a buried, vertical split gate memory device. U.S. Pat. No. 6,204,126 B1 to Hsieh et al discloses a split gate flash cell formed with word line spacers. U.S. Pat. No. 6,143,606 to Wang et al shows a split gate flash memory cell.
A principal object of the present invention is to provide an effective and very manufacturable method to form split gate flash memory cells and a novel split gate flash memory cell device in an integrated circuit device.
A further object of the present invention is to provide a method to form split gate memory cells with word line spacers having improved width control.
A yet further object of the present invention is to provide a method having improved salicide capability.
A yet further object of the present invention is to provide a method that does not require a masking level for defining the word line spacers.
A further object of the present invention is to provide a split gate device having improved word line width control.
A yet further object of the present invention is to provide a split gate device having improved salicide capability.
In accordance with the objects of this invention, a method to form split gate flash memory cells in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. Pairs of floating gates are formed overlying the substrate. Common source plugs are formed overlying the substrate and filling spaces between the floating gate pairs. An oxide layer is formed overlying the substrate, the floating gates, and the common source plugs. A conductor layer is deposited overlying the oxide layer. First dielectric spacers are formed on vertical surfaces of the conductor layer. The conductor layer is etched through where not covered by the first dielectric spacers to thereby form word line gates adjacent to the floating gates. Second dielectric spacers are formed on vertical surfaces of the word line gates and the first dielectric spacers to complete the split gate flash memory cells.
Also in accordance with the objects of this invention, a split gate flash memory cell device is achieved. The device comprises a substrate. A pair of floating gates overlies the substrate. A common source plug overlies the substrate and filling spaces between the floating gate pair. A pair of word line gates each comprises, first, a polysilicon layer overlying the substrate and adjacent to one of the floating gates with an oxide layer therebetween. Second, a first dielectric spacer is on a vertical surface of the polysilicon layer. Finally, a second dielectric spacer is on a vertical surface of the polysilicon layer and of the first dielectric spacer. A pair of bit line drains is self-aligned to the word line gates.